A low-power VLSI arrhythmia classifier

Author

Leong, Philip H W ; Jabri, Marwan A.

Author_Institution

Dept. of Electr. Eng., Sydney Univ., NSW, Australia

Volume

6

Issue

6

fYear

1995

fDate

11/1/1995 12:00:00 AM

Firstpage

1435

Lastpage

1445

Abstract

The design, implementation, and operation of a low-power multilayer perceptron chip (Kakadu) in the framework of a cardiac arrhythmia classification system is presented in this paper. This classifier, called MATIC, makes timing decisions using a decision tree, and a neural network is used to identify heartbeats with abnormal morphologies. This classifier was designed to be suitable for use in implantable devices and a VLSI (very large scale integration) neural-network chip (Kakadu) was designed so that the computationally expensive neural-network algorithm can be implemented with low power consumption. Kakadu implements a (10,6,4) perceptron and has a typical power consumption of tens of microwatts. When used with the arrhythmia classification system, the chip can operate with an average power consumption of less than 25 nW

Keywords

VLSI; defibrillators; learning (artificial intelligence); medical signal processing; multilayer perceptrons; neural chips; pattern classification; Kakadu; MATIC; abnormal morphologies; decision tree; implantable devices; low-power VLSI arrhythmia classifier; low-power multilayer perceptron chip; neural network; timing decisions; Australia; Classification algorithms; Energy consumption; Heart rate; Medical treatment; Morphology; Multilayer perceptrons; Neural networks; Very large scale integration; Voltage;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.471380

Filename

471380