Title :
On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
When storage requirements or limits on test application time do not allow a complete (compact) test set to be used for a circuit, a partial test set that detects as many faults as possible is required. Motivated by this application, we address the following problem. Given a test sequence T of length L for a synchronous sequential circuit and a length MS of length at most M such that the fault coverage of TS is maximal. A similar problem was considered before for combinational and scan circuits and solved by test ordering. Test ordering is not possible with the single test sequence considered here for sequential circuits. We solve this problem by using a vector omission process that allows the length of the sequence T to be reduced while allowing minimal reductions in the number of detected faults. Using this process, it is possible to obtain a sequence TS that has the desired length and a maximal fault coverage.
Keywords :
circuit testing; combinational circuits; fault diagnosis; logic testing; sequential circuits; combinational circuits; fault coverage; scan circuits; storage requirements; synchronous sequential circuit; test application time; test compaction; test sequence; vector omission process; Circuit faults; Circuit testing; Combinational circuits; Compaction; Electrical fault detection; Fault detection; Helium; Sequential analysis; Sequential circuits; 65; Index Terms- Synchronous sequential circuits; test application time; test compaction.;
Journal_Title :
Computers, IEEE Transactions on