• DocumentCode
    1035077
  • Title

    Fast parallel-prefix modulo 2n+1 adders

  • Author

    Efstathiou, Costas ; Vergos, Haridimos T. ; Nikolos, Dimitris

  • Author_Institution
    Informatics Dept., TEI of Athens, Greece
  • Volume
    53
  • Issue
    9
  • fYear
    2004
  • Firstpage
    1211
  • Lastpage
    1216
  • Abstract
    Modulo 2n+1 adders find great applicability in several applications including RNS implementations and cryptography. In this paper, we present two novel architectures for designing modulo 2n+1 adders, based on parallel-prefix carry computation units, the first architecture utilizes a fast carry increment stage, whereas the second is a totally parallel-prefix solution. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and execution latency.
  • Keywords
    adders; carry logic; logic gates; parallel architectures; residue number systems; CMOS implementations; RNS implementations; binary adders; cryptography; parallel-prefix carry computation units; parallel-prefix modulo 2n+1 adders; Adders; Arithmetic; Computer architecture; Concurrent computing; Cryptography; Delay; Digital filters; Discrete Fourier transforms; Discrete cosine transforms; Fourier transforms; 65; Index Terms- Binary adders; RNS.; modulo 2^n+1 arithmetic; parallel-prefix adders;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2004.60
  • Filename
    1315614
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1035077