Method for synthesis of MOSFET logic networks

A method is described for synthesis of single-output MOSFET logic networks from functional specifications (including `don´t-cares¿), based on the restriction that circuit inputs connect only to MOSFET gates (and vice versa). Every distinct combination of input terminal orderings is assessed in the search for an optimal solution. As the potential search space is factorial in the input dimension, heuristics are employed to bypass the synthesis of inefficient circuits. The ability to override these heuristics and force terminal orderings allows external as well as internal issues to influence selection.