Title :
Reply to “Comments on the optimum CMOS tapered buffer problem”
Author_Institution :
UNISYS Corp., San Diego, CA, USA
fDate :
2/1/1994 12:00:00 AM
Abstract :
For original article see ibid., vol 27, p. 118-9 (1992). For comments on original paper see ibid., vol29, no. 2, p155-8 (1994). The optimum tapered buffer has been extensively discussed in the literature. In this correspondence a general model is derived and it is shown that previously reported models are specific cases of the general model presented here
Keywords :
CMOS integrated circuits; buffer circuits; integrated logic circuits; logic gates; general model; inverters; logic gates; optimum CMOS tapered buffer; CMOS technology; Capacitance; Curve fitting; Delay effects; Delay lines; Equations; Inverters; Numerical simulation; Semiconductor device modeling; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
