An in-place architecture for the deblocking filter in H.264/AVC

Author

Cheng, Chao-Chung ; Chang, Tian-Sheuan ; Lee, Kun-Bin

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

53

Issue

7

fYear

2006

fDate

7/1/2006 12:00:00 AM

Firstpage

530

Lastpage

534

Abstract

This brief presents an in-place computing design for the deblocking filter used in H.264/AVC video coding standard. The proposed in-placed computing flow reuses intermediate data as soon as data is available. Thus, the intermediate data storage is reduced to only the four 4 × 4 blocks instead of whole 16 × 16 macroblock. The resulting design can achieve 100 MHz with only 13.41K gate count and support real-time deblocking operation of 2K × 1K@30 Hz video application when clocked at 73.73 MHz by using 0.25-μm CMOS technology.

Keywords

CMOS digital integrated circuits; digital filters; logic design; video coding; 0.25 micron; 100 MHz; 30 Hz; 73.73 MHz; CMOS technology; H.264/AVC; VLSI architecture design; deblocking filter; intermediate data storage; real-time deblocking; video coding standard; Automatic voltage control; Bandwidth; CMOS technology; Computer architecture; Data flow computing; Filters; Memory; Transform coding; Very large scale integration; Video coding; Deblocking filter; H.264/AVC; VLSI architecture design;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2006.875323

Filename

1658183