Kickback noise reduction techniques for CMOS latched comparators

Author

Figueiredo, Pedro M. ; Vital, João C.

Author_Institution

Chipidea Microelectron. SA, Porto Salvo, Portugal

Volume

53

Issue

7

fYear

2006

fDate

7/1/2006 12:00:00 AM

Firstpage

541

Lastpage

545

Abstract

The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-μm technology demonstrate their effectiveness.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); integrated circuit noise; 0.18 micron; CMOS latched comparators; HSPICE simulations; analog input signal; analog-to-digital converter; full-scale digital level; kickback noise reduction; positive feedback mechanism; CMOS technology; Circuits; Degradation; Feedback; Inverters; Noise generators; Noise reduction; Power dissipation; Switches; Voltage; Analog–digital conversion; CMOS; kickback noise; latched comparator;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2006.875308

Filename

1658186