DocumentCode
1037096
Title
Perfect shifters [multiprocessor interconnection networks]
Author
Fiduccia, Charles M. ; Rappoport, Kevin J.
Author_Institution
Supercomputing Res. Center, Bowie, MD, USA
Volume
43
Issue
3
fYear
1994
fDate
3/1/1994 12:00:00 AM
Firstpage
340
Lastpage
349
Abstract
Pin-efficient single-instruction multiple-data networks, with p≈√(2m) pins per cell that can-in one clock tick-shift data by any amount k in an interval [-m,m] are considered. Perfect barrel shifters, which perform the group of permutations c→c+k(mod n), 0⩽k⩽n-1, using p=q+1 pins per cell, are known to exist for all n=q2+q+1, where q is any prime power. In sharp contrast, it is shown that for any permutation π of order greater than 3m, one-tick perfect shifters for the set of permutations π[-m,m] ={πk|-m⩽k⩽m} exist only for the three cases (m=1, p=2), (m=3, p=3), and (m=6, p=4). In particular, only three perfect linear arrays, c→c+k, exist. The proof is based on a relationship between the difference covers and zero-one solutions to certain quadratic equations
Keywords
multiprocessor interconnection networks; parallel algorithms; parallel architectures; difference covers; perfect linear arrays; perfect shifters; permutations; quadratic equations; single-instruction multiple-data networks; zero-one solutions; Clocks; Difference equations; Fabrication; Multiprocessor interconnection networks; Parallel processing; Pins; Shift registers; Very large scale integration;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.272434
Filename
272434
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