Title :
Fault-tolerant schemes for parallel architectures
Author :
Livesey, M.J. ; Owczarczyk, J.
Author_Institution :
University of St. Andrews, Department of Computational Scienc, St. Andrews, UK
Abstract :
Fault-tolerance schemes for efficient implementation in parallel VLSI processors are discussed, and a modular approach for tree and mesh-structured architectures is described
Keywords :
fault tolerant computing; parallel architectures; efficient implementation; fault tolerant computing; mesh-structured architectures; modular approach; parallel VLSI processors; parallel architectures;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19870839
