A novel multiplexer-based low-power full adder

Author

Jiang, Yingtao ; Al-Sheraidah, Abdulkarim ; Wang, Yuke ; Sha, Edwin ; Chung, Jin-Gyun

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Nevada, Las Vegas, NV, USA

Volume

51

Issue

7

fYear

2004

fDate

7/1/2004 12:00:00 AM

Firstpage

345

Lastpage

348

Abstract

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.

Keywords

VLSI; adders; application specific integrated circuits; circuit simulation; integrated circuit design; low-power electronics; multiplexing equipment; CMOS adder; HSPICE simulation; VLSI circuit; application specific integrated circuits design; low-power full adder; multiplexer; power savings; very large-scale integrated circuit; Adders; Application specific integrated circuits; CMOS logic circuits; Circuit simulation; Computer science; Energy consumption; Multiplexing; Recycling; Testing; Very large scale integration; Full adder; VLSI; circuit; low power; multiplexer; very large-scale integrated;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2004.831429

Filename

1315882