Real-time data sparsification for the SLD vertex detector

The charge-coupled device (CCD)-based vertex detector for SLD (the Stanford Linear Detector) will generate a prodigious volume of data for each trigger. A powerful signal-processing technique that uses pipelined ASIC (application-specific integrated circuits) processors to filter the data in real time is described. This cluster processor technique is designed to extract the CCD image signal from the readout noise efficiently and in real time without producing an excessive volume of unwanted noise data. By operating `on the fly,´ and with extensive use of pipelining, dead-time effects are independent of the volume of data and are entirely negligible