Real-time data sparsification for the SLD vertex detector

Author

Damerell, C J S ; Gillman, A.R. ; Phillips, D.A.

Author_Institution

Rutherford Appleton Lab., Chilton, Didcot, UK

Volume

37

Issue

2

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

305

Lastpage

309

Abstract

The charge-coupled device (CCD)-based vertex detector for SLD (the Stanford Linear Detector) will generate a prodigious volume of data for each trigger. A powerful signal-processing technique that uses pipelined ASIC (application-specific integrated circuits) processors to filter the data in real time is described. This cluster processor technique is designed to extract the CCD image signal from the readout noise efficiently and in real time without producing an excessive volume of unwanted noise data. By operating `on the fly,´ and with extensive use of pipelining, dead-time effects are independent of the volume of data and are entirely negligible

Keywords

particle detectors; physics computing; CCD image signal; SLD vertex detector; Stanford Linear Detector; application-specific integrated circuits; charge-coupled device; dead-time effects; on the fly operation; pipelined ASIC; pipelining; readout noise; real-time data sparsification; signal-processing technique; trigger; Application specific integrated circuits; Charge coupled devices; Data mining; Detectors; Filters; Integrated circuit noise; Process design; Signal design; Signal processing; Superluminescent diodes;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.106635

Filename

106635