Title :
A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays
Author :
Arora, V. ; Jone, W.B. ; Huang, D.C. ; Das, S.R.
Author_Institution :
Dept. of Electr. & Comput. Eng. & Comput. Sci., Univ. of Cincinnati, OH, USA
Abstract :
In this paper, we propose a built-in self-diagnostic march-based algorithm that identifies faulty memory cells based on a recently introduced nontraditional fault model. It is developed based on the DiagRSMarch algorithm, which is a diagnostic algorithm to identify traditional faults for embedded memory arrays. A minimal set of additional operations is added to DiagRSMarch for identifying the nontraditional faults without affecting the diagnostic coverage of the traditional faults. The embedded memory arrays are accessed using a bidirectional serial interfacing architecture which minimizes the routing overhead introduced by the diagnosis hardware. Using the concepts of the bidirectional interfacing technique, parallel testing, and redundant-tolerant operations, the diagnostic process can be accomplished efficiently at-speed with minimal hardware overhead.
Keywords :
automatic test pattern generation; built-in self test; fault diagnosis; integrated memory circuits; memory architecture; system-on-chip; DiagRSMarch algorithm; bidirectional interfacing technique; built-in self-diagnostic method; diagnostic algorithm; diagnostic coverage; diagnostic process; embedded memory rays; nontraditional fault model; parallel testing; redundant-tolerant operations; Built-in self-test; Computer science; Fault diagnosis; Hardware; Logic arrays; Logic testing; Random access memory; Redundancy; Routing; Wires; Built-in self-diagnosis; embedded memory array testing; march algorithms; nontraditional memory fault model; serial interfacing technique;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
DOI :
10.1109/TIM.2004.830785