DocumentCode :
1038767
Title :
Plated wire 200-ns main memory
Author :
Nitta, Matsuo ; Ishii, Osamu ; Takashima, Minoru
Author_Institution :
Electrotechnical Laboratory of the japanese Government, Tokyo, Japan
Volume :
4
Issue :
4
fYear :
1968
fDate :
12/1/1968 12:00:00 AM
Firstpage :
675
Lastpage :
678
Abstract :
A 4-K-word 50-bit-per-word plated wire main memory was constructed and tested at a 200-ns cycle time. 32 matrix planes were constructed of the woven wire type (each plane contained 128 words and was stacked into 2 blocks for a total capacity of 4 K words). Special design features for high-speed operations are 1) memory stack construction with memory planes which are serially connected with grounded conductors, 2) balanced word line driving using transmission-line-type transformers, 3) bridge configuration of the digit-sense system, and 4) digit driving scheme using nonreturn-to-zero current. Operating margins of the system were tested with an account being taken of the effect of magnetic domain wall creeping for more than 106 disturb pulses.
Keywords :
Plated-wire memories; Conductors; Diodes; Government; Magnetic cores; Pulse amplifiers; Switches; Timing; Transformer cores; Transmission line matrix methods; Wire;
fLanguage :
English
Journal_Title :
Magnetics, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9464
Type :
jour
DOI :
10.1109/TMAG.1968.1066376
Filename :
1066376
Link To Document :
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