Crosstalk test pattern generation for dynamic programmable logic arrays

Crosstalk noise is one of the major noise problems introduced by interconnect wire scaling and high clock speed. In modern deep submicrometer circuits (DSM), signal crosstalk can arise between two long parallel wires. Programmable logic arrays (PLAs) are important building blocks in digital very large scale integrated (VLSI) circuits; especially, dynamic PLAs have been used pervasively in modern high-speed circuit design because of their predictable delays. However, a dynamic PLA may suffer crosstalk noises that will cause the circuit to malfunction due to charge loss. In this paper, based on the characteristics of dynamic PLA crosstalk noise, an automatic test pattern generation (ATPG) method to detect the maximum crosstalk noise for each product line is presented. Test patterns are then compressed by a test pattern compressor. Experimental results obtained by simulating Microelectronics Center of North Carolina (MCNC) PLA benchmark circuits demonstrate the efficiency of the ATPG and test compression methods