Title :
Low-Cost Scan Test for IEEE-1500-Based SoC
Author :
Yi, Hyunbean ; Song, Jaehoon ; Park, Sungju
Author_Institution :
Hanyang Univ., Ansan
fDate :
5/1/2008 12:00:00 AM
Abstract :
In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE- 1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experiments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing.
Keywords :
automatic test equipment; integrated circuit testing; system-on-chip; IEEE-1149.1 TAP; IEEE-1500-based SoC; low-cost automated test equipment; on-chip test clock generator; scan delay test; system-on-chip; Delay test; IEEE 1500; design-for-testability (DfT); reduced pin-count test (RPCT); system-on-a-chip (SoC);
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
DOI :
10.1109/TIM.2007.911699
