Block-oriented programmable design with switching network interconnect

Author

Yeh, Ching-Wei ; Liu, Lung-Tien ; Cheng, Chung-Kuan ; Hu, T.C. ; Ahmed, Syed ; Liddel, Michael

Author_Institution

Nat. Chung-Cheng Univ., Taiwan

Volume

2

Issue

1

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

45

Lastpage

53

Abstract

A block-oriented programmable design with switching network interconnect is proposed for fast turn-around, low manufacturing cost, and layout-independent high-speed systems. We introduce the architecture and investigate the constraints and properties originated from the architecture. We show that routability is the most crucial concern for a successful design, and propose objective functions as well as algorithms for switching network optimization. The mapping for the circuits is performed by partitioning, placement, and routing using a maximum matching method. The integration of the whole system demonstrates excellent results in terms of circuit usage.<>

Keywords

circuit layout CAD; logic CAD; logic arrays; network routing; switching networks; block-oriented programmable design; circuit mapping; fast turn-around; layout automation; layout-independent high-speed systems; maximum matching method; objective functions; partitioning; placement; routability; switching network interconnect; switching network optimization; Algorithm design and analysis; Costs; Integrated circuit interconnections; Macrocell networks; Manufacturing; Pins; Programmable logic arrays; Propagation delay; Routing; Upper bound;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.273149

Filename

273149