DocumentCode
1039409
Title
Rate-optimal DSP synthesis by pipeline and minimum unfolding
Author
Jeng, Lih-Gwo ; Chen, Liang-Gee
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
2
Issue
1
fYear
1994
fDate
3/1/1994 12:00:00 AM
Firstpage
81
Lastpage
88
Abstract
This paper presents a rate-optimal scheduling for real-time DSP algorithms. By using pipelining and unfolding techniques, the parallel characteristics of recursive DSP algorithms can be exploited. A novel unfolding technique is developed to unravel all concurrency in the recursive data flow graph. A perfect rate unfolded data flow graph is also introduced, which can cause a fully static rate optimal functional pipeline schedule. Experimental results have shown that the proposed method can always yield rate-optimal designs with a smaller unfolding factor compared to previous studies.<>
Keywords
digital filters; digital signal processing chips; graph theory; logic CAD; pipeline processing; fully static rate optimal functional pipeline schedule; minimum unfolding; parallel characteristics; perfect rate unfolded data flow graph; pipelining; rate-optimal DSP synthesis; rate-optimal scheduling; real-time DSP algorithms; recursive DSP algorithms; recursive data flow graph; Delay; Digital signal processing; Digital signal processing chips; Flow graphs; Optimal scheduling; Pipelines; Processor scheduling; Scheduling algorithm; Signal processing algorithms; Telecommunication computing;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.273152
Filename
273152
Link To Document