Title :
Formal verification of timed systems: a survey and perspective
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
An overview of the current state of the art of formal verification of real-time systems is presented. We discuss commonly accepted models, specification languages, verification frameworks, state-space representation schemes, state-space construction procedures, reduction techniques, pioneering tools, and finally some new related issues. We also make a few comments according to our experience with verification tool design and implementation.
Keywords :
embedded systems; formal verification; reviews; specification languages; state-space methods; temporal logic; formal verification; pioneering tools; real time systems; reduction technique; specification language; state space construction procedure; state space representation; temporal logic; timed systems; verification framework; Clocks; Costs; Data structures; Formal verification; Logic; Mathematical model; Polynomials; Real time systems; Specification languages; Very large scale integration; Embedded systems; formal methods; formal verification; models; real-time systems; specification; temporal logics; theory; tools;
Journal_Title :
Proceedings of the IEEE
DOI :
10.1109/JPROC.2004.831197
