The Scalable Coherent Interface, IEEE P 1596, status and possible applications to data acquisition and physics

Author

Gustavson, David B.

Author_Institution

Stanford Linear Accel. Center, CA, USA

Volume

37

Issue

2

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

365

Lastpage

368

Abstract

IEEE P 1596, the Scalable Coherent Interface (SCI) (formerly known as SuperBus), is based on experience gained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), Futurebus (IEEE P896.x), and other modern 32-b buses. SCI goals include a minimum bandwidth of 1 GB/s per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of distributed shared memory; support for repeaters which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks. Current directions are summarized, and the status of work in progress is reported. Some applications in data acquisition and physics are suggested

Keywords

data acquisition; nuclear electronics; physics computing; 32-b buses; ANSI/IEEE 960-1986; Banyan; Futurebus; IEC 935; IEEE P 1596; Omega; Scalable Coherent Interface; SuperBus; crossbar networks; data acquisition; distributed shared memory; distributed-cache image; minimum bandwidth; multiprocessor systems; processor; repeaters; Computer aided manufacturing; Computer networks; Data acquisition; Hardware; Integrated circuit interconnections; Integrated circuit technology; Physics; Power system interconnection; Supercomputers; Switches;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.106646

Filename

106646