A DSP architectural design for low bit-rate motion video codec

Author

Murakami, Tokumichi ; Kamizawa, Koh ; Kameyama, Masatoshi ; Nakagawa, Shin-ichi

Author_Institution

Mitsubishi Electr. Corp., Kamakura, Japan

Volume

36

Issue

10

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1267

Lastpage

1274

Abstract

A new digital signal processor (DSP) architecture is presented. This DSP consists of the usual components, such as instruction set, buses, data memories, execution unit, address generators, sequencer, and direct memory access controller, optimized for video signal processing. A 24-bit 50-ns DSP called the digital image signal processor (DISP) has been developed using 1-μm CMOS technology. The performance of the DSP is evaluated by a benchmark test based on an actual video coding sequence. A multi-DSP configuration for a video codec that allows flexible algorithms and variable picture formats is studied. A low-bit-rate motion video codec can be built very easily using the DSPs presented by the authors

Keywords

CMOS integrated circuits; VLSI; codecs; computerised signal processing; digital signal processing chips; telecommunications computing; video equipment; video signals; visual communication; 1 micron; 24 bit; 50 ns; CMOS technology; DISP; DSP architectural design; VLSI chip; address generators; data memories; digital image signal processor; digital signal processor; direct memory access controller; execution unit; instruction set; low bit-rate motion; multi-DSP configuration; sequencer; variable picture formats; video codec; video coding; video signal processing; visual communication; Benchmark testing; CMOS process; CMOS technology; Digital images; Digital signal processing; Digital signal processors; Signal generators; Signal processing; Video codecs; Video signal processing;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.44342

Filename

44342