A VLSI architecture for a pel recursive motion estimation algorithm

Motivated by a growing demand for an efficient motion compensated (MC) coder operating in real time, the authors propose a VLSI architecture based on parallel and pipelined processing for implementing the pel-recursive motion estimation algorithm for predictive coding of time-varying images. In order to maximize the processing concurrency, the displacement estimation process is divided into its integer and fractional part calculations, and the displacement estimation and the interpolation calculations are decoupled so that each calculation can be computed on a separate processor. The proposed architecture, which exploits pipelining, parallelism, and simple adjacent-neighbor interprocessor wiring, is appropriate for VLSI implementation. The performance of the proposed architecture on the real image sequences is evaluated. Issues regarding the fixed-point arithmetic and coding are discussed