Title :
Array architectures for block matching algorithms
Author :
Komarek, Thomas ; Pirsch, Peter
Author_Institution :
Inst. fuer Theor. Nachrichtentech. und Inf., Hannover Univ., West Germany
fDate :
10/1/1989 12:00:00 AM
Abstract :
A description is given of VLSI architectures for block-matching algorithms utilizing systolic array processors. A well-known mapping procedure has been applied to derive the array processors from the algorithm. Examples of two- and one-dimensional systolic arrays are presented. The transistor-count of the architectures using presently available CMOS technology and their maximum processable frame rates for real-time computation of video signals have been estimated
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; computerised picture processing; digital signal processing chips; parallel architectures; real-time systems; telecommunications computing; video signals; 1D array; 2D array; CMOS technology; TV signals; VLSI architectures; block matching algorithms; mapping procedure; parallel processing; real-time computation; systolic array processors; video signals; videotelephony; CMOS process; CMOS technology; Computer architecture; Hardware; Image coding; Motion estimation; Shape; Signal processing; Systolic arrays; Very large scale integration;
Journal_Title :
Circuits and Systems, IEEE Transactions on
