A family of VLSI designs for the motion compensation block-matching algorithm

A family of modular VLSI architectures and chip implementations of the motion-compensation full-search block-matching algorithm are described. This set of application-specific integrated circuits is motivated by the intensive computations required to perform motion compensation in real time. The architectures are based on data-flow designs, which allow sequential inputs but perform parallel processing with 100% efficiency. On the basis of these architectures, a programmable chip can be designed for motion vector estimation with different block sizes. The chips can be cascaded for a larger tracking range or for a video source with a higher pixel sampling rate. A chip-pair design is also derived for calculating fractional motion vectors with quarter-pel precision. The chip-pair design has been laid out, and the chip characteristics are given. Test circuitry is also included to increase the testability of the chips