Computer-aided crosstalk minimisation design for system-on-chip

Crosstalk caused by coupling capacitance is a major source of load and delay faults in ultra-deep submicron system-on-chip (SoC). Minimising such faults is important to the performance and reliability of SoC designs. A novel computer-aided crosstalk minimisation design for the SoC is presented. A divide-and-conquer method to rearrange wire segments is used such that the coupling length can be minimised. Next, the space between adjacent tracks is adjusted using a quadratic programming method. The proposed design on the AMBA-based SoC platform is implemented and provided experimental results to demonstrate the effectiveness of the method.