• DocumentCode
    1041456
  • Title

    Effects of device scaling and geometry on MOS radiation hardness assurance

  • Author

    Shaneyfelt, M.R. ; Fleetwood, D.M. ; Winokur, P.S. ; Schwank, J.R. ; Meisenheimer, T.L.

  • Author_Institution
    Sandia Nat. Lab., Albuquerque, NM, USA
  • Volume
    40
  • Issue
    6
  • fYear
    1993
  • fDate
    12/1/1993 12:00:00 AM
  • Firstpage
    1678
  • Lastpage
    1685
  • Abstract
    The effects of transistor scaling and geometry on radiation hardness are investigated. The total-dose response is shown to depend strongly on transistor channel length. Specifically, transistors with shorter gate lengths tend to show more negative threshold-voltage shifts under irradiation than transistors with longer gate lengths. Similarly, transistors with longer gate lengths tend to show more positive threshold-voltage shifts during postirradiation annealing. It will be important to factor these differences in radiation response into test-structure-to-IC correlations necessary to support cost-effective qualified manufacturers list hardness assurance. Transistors with minimum gate length will have a larger effect on standby power supply current for an IC at high dose rates, such as in a weapon environment, where worst-case response is associated with negative threshold-voltage shifts during irradiation. On the other hand, transistors with maximum gate length will have a larger effect on the timing parameters of an IC at low dose rates, such as in a space environment
  • Keywords
    CMOS integrated circuits; MOS integrated circuits; X-ray effects; annealing; insulated gate field effect transistors; radiation hardening (electronics); random noise; semiconductor device noise; semiconductor device testing; 1/f noise; MOS radiation hardness assurance; X-ray irradiation; channel length; gate lengths; geometry; postirradiation annealing; space environment; standby power supply current; test-structure-to-IC correlations; threshold-voltage shifts; timing parameters; total-dose response; transistor scaling; weapon environment; worst-case response; Annealing; CMOS technology; Circuit testing; Geometry; Integrated circuit testing; Laboratories; Logic testing; Manufacturing; Timing; Weapons;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.273493
  • Filename
    273493