Title :
Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding
Author :
Martina, Maurizio ; Nicola, Mario ; Masera, Guido
Author_Institution :
Dipt. di Elettron., Politec. di Torino, Torino
fDate :
11/1/2008 12:00:00 AM
Abstract :
A low complexity, parallel, collision-free interleaver architecture for the WiMax duo-binary turbo decoder is presented. The proposed architecture dynamically adapts to different block sizes and it features reduced complexity resorting to parallel circular shifting interleavers. Moreover, it sustains a peak throughput of nearly 90 Mb/s with a 200 MHz clock frequency, when synthesized on a 0.13 mum standard cell technology.
Keywords :
WiMax; binary codes; decoding; interleaved codes; turbo codes; WiMax; bit rate 90 Mbit/s; duo-binary decoding; frequency 200 MHz; hardware design; low complexity; parallel circular shifting interleavers; parallel interleaver decoding; size 0.13 mum; turbo decoding; Clocks; Code standards; Communication standards; Frequency synthesizers; Hardware; Iterative decoding; Read-write memory; Throughput; Very large scale integration; WiMAX; Parallel interleaver, hardware, VLSI;
Journal_Title :
Communications Letters, IEEE
DOI :
10.1109/LCOMM.2008.081113
