Title :
Robust interfaces for mixed-timing systems
Author :
Chelcea, Tiberiu ; Nowick, Steven M.
Author_Institution :
Columbia Univ., New York, NY, USA
Abstract :
This paper presents several low-latency mixed-timing FIFO (first-in-first-out) interfaces designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The designs are then adapted to work between systems with very long interconnect delays, by migrating a single-clock solution by Carloni et al. (1999, 2000, and 2001) (for "latency-insensitive" protocols) to mixed-timing domains. The new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initial simulations for both latency and throughput are promising.
Keywords :
delay circuits; digital integrated circuits; integrated circuit design; integrated circuit modelling; synchronisation; system-on-chip; timing circuits; asynchronous system; interconnect delays; interface operating speeds; interface systems on chip; latency insensitive protocols; low latency mixed timing first-in-first-out interfaces; low-latency mixed-timing FIFO interfaces designs; metastability; mixed timing domains; mixed-timing systems; robust interfaces; single clock solution; synchronous system; Clocks; Computer science; Delay; Frequency synchronization; Integrated circuit interconnections; Metastasis; Protocols; Robustness; Timing; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2004.831476
