A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

Author

Bashirullah, Rizwan ; Liu, Wentai ; Cavin, Ralph ; Edwards, Dale

Author_Institution

Dept. of Electr. Eng., North Carolina State Univ., Raleigh, NC, USA

Volume

12

Issue

8

fYear

2004

Firstpage

876

Lastpage

880

Abstract

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.

Keywords

CMOS integrated circuits; current-mode circuits; integrated circuit interconnections; integrated circuit testing; repeaters; system-on-chip; CMOS integrated circuits; RC interconnect static bus; adaptive bandwidth bus architecture; adaptive bandwidth capability; hybrid current-voltage mode repeaters; hybrid current/voltage mode on-chip signaling scheme; static power dissipation; voltage mode signaling; Bandwidth; Delay; Design automation; Frequency; Integrated circuit interconnections; Power dissipation; Repeaters; Very large scale integration; Voltage; Wire;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2004.831481

Filename

1316902