Electrical Behavior and Technology Optimization of Si/SiGeC HBTs on Thin-Film SOI

Author

Avenier, Grégory ; Fregonese, Sebastien ; Chevalier, Pascal ; Bustos, Jessy ; Saguin, Fabienne ; Schwartzmann, Thierry ; MANEUX, Cristell ; Zimmer, Thomas ; Chantre, Alain

Author_Institution

STMicroelectron., Crolles

Volume

55

Issue

2

fYear

2008

Firstpage

585

Lastpage

593

Abstract

A growing interest has been focused on silicon on insulator (SOI) technologies over the past years. Yet, few studies were carried out regarding the integration of vertical SiGe heterojunction bipolar transistors (HBTs) using such substrates. This paper deals both with the integration of a SiGeC HBT on thin-film CMOS-compatible SOI, and a comprehensive study of its electrical behavior based on physical simulation and electrical characterization. Various aspects of the optimization of device performances are described, considering process or layout improvements.

Keywords

CMOS integrated circuits; Ge-Si alloys; avalanche breakdown; heterojunction bipolar transistors; silicon; silicon compounds; silicon-on-insulator; CMOS-compatible SOI; HBT; SiGeC; avalanche breakdown; electrical behavior; heterojunction bipolar transistors; integrated circuit fabrication; silicon on insulator technologies; silicon-on-insulator technology; technology optimization; thin-film SOI; BiCMOS integrated circuits; CMOS technology; Circuit simulation; Fabrication; Heterojunction bipolar transistors; Integrated circuit technology; Isolation technology; Semiconductor thin films; Silicon on insulator technology; Substrates; Avalanche breakdown; heterojunction bipolar transistors (HBTs); integrated circuit fabrication; silicon on insulator (SOI) technology; simulation;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2007.912361

Filename

4435991