Title :
Architecture of a high speed Reed-Solomon decoder
Author :
Iwaki, Tetsuo ; Tanaka, Toshihisa ; Yamada, Eiji ; Okuda, Tohru ; Sasada, Taizoh
Author_Institution :
Sharp Corp., Nara, Japan
fDate :
2/1/1994 12:00:00 AM
Abstract :
The authors propose an architecture for an error correction circuit suitable for high-rate data decoding of the Reed-Solomon code. It features a multiple-error correction capability of 4 errors or 8 erasures. The operational steps for multiple-error decoding are reduced by a 4-stage pipeline and a superscalar processor of a Galois field. The experimental circuit´s 16 Mbyte/s rate of data decoding is sufficient for compressed video signals of high-definition as well as those of standard-definition TVs
Keywords :
Reed-Solomon codes; decoding; error correction codes; high definition television; parallel processing; pipeline processing; video signals; video tape recorders; 4-stage pipeline processor; Galois field; architecture; compressed video signals; error correction circuit; high speed Reed-Solomon decoder; high-rate data decoding; multiple-error correction capability; multiple-error decoding; standard-definition TV; superscalar processor; Circuits; Decoding; Error correction; Error correction codes; Galois fields; HDTV; High definition video; Pipelines; Reed-Solomon codes; Video compression;
Journal_Title :
Consumer Electronics, IEEE Transactions on
