DocumentCode
1042898
Title
A divide-and-conquer algorithm for 3-D capacitance extraction
Author
Shi, Weiping ; Yu, Fangqing
Author_Institution
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Volume
23
Issue
8
fYear
2004
Firstpage
1157
Lastpage
1163
Abstract
We present a divide-and-conquer algorithm to improve the three-dimensional (3-D) boundary element method (BEM) for capacitance extraction. We divide large interconnect structures into small sections, set new boundary conditions using the border for each section, solve each section, and then combine the results to derive the capacitance. The target application is critical nets, clock trees, or packages where 3-D accuracy is required. Our algorithm is a significant improvement over the traditional BEMs and their enhancements, such as the "window" method, where conductors far away are dropped, and the "shield" method where conductors hidden behind other conductors are dropped. Experimental results show that our algorithm is a magnitude faster than the traditional BEM and the window+shield method, for medium to large structures. The error of the capacitance computed by the new algorithm is within 2% for self capacitance and 7% for coupling capacitance, compared with the results obtained by solving the entire system using BEM. Furthermore, our algorithms gives accurate distributed RC, where none of the previous 3-D BEM algorithms and their enhancements can.
Keywords
boundary-elements methods; capacitance; divide and conquer methods; integrated circuit interconnections; 3D boundary element method; 3D capacitance extraction; BEM; boundary conditions; clock trees; conductors; coupling capacitance; critical nets; divide-and-conquer algorithm; interconnect structures; parasitic extraction; self capacitance; shield method; window method; Approximation algorithms; Boundary element methods; Clocks; Conductors; Equations; Geometry; Integrated circuit interconnections; Iterative algorithms; Linear systems; Parasitic capacitance; BEM; Boundary element method; capacitance extraction; parasitic extraction;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2004.831595
Filename
1316996
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