Statistical clock skew analysis considering intradie-process variations

With shrinking cycle times, clock skew has become an increasingly difficult and important problem for high performance designs. Traditionally, clock skew has been analyzed using case-files which cannot model intradie-process variations and hence result in a very optimistic skew analysis. In this paper, we present a statistical skew analysis method to model intradie process variations. We first present a formal model of the statistical clock-skew problem and then propose an algorithm based on propagation of joint probability density functions in a bottom-up fashion in a clock tree. The analysis accounts for topological correlations between path delays and has linear runtime with the size of the clock tree. The proposed method was tested on several large clock-tree circuits, including a clock tree from a large industrial high-performance microprocessor. The results are compared with Monte Carlo simulation for accuracy comparison and demonstrate the need for statistical analysis of clock skew.