Title :
A multi-probe approach for MCM substrate testing
Author :
So-Zen Yao ; Chou, Nan-Chi ; Cheng, Chung-Kuan ; Hu, T.C.
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
fDate :
1/1/1994 12:00:00 AM
Abstract :
Multi-chip module (MCM) technology has become an important means to package high performance systems. An important task during the packaging process is to check for possible open, short, and high resistance faults in the wiring networks of the bare MCM substrates, which is called substrate testing. After examining several substrate testing methodologies, we find that multi-probe or k-probe testers are cost-effective for substrate testing. However, the testing speed of this method is not high; hence, we focus on improving the throughput by reducing the number of tests and by deriving good probe routes. For test size reduction, we propose a routing tree model to capture the wiring structure of a given net; then by taking advantage of the routing tree, we generate a minimum number of tests while ensuring complete open fault coverage. Our algorithm reduces the number of tests by up to 50% compared to that of previous approaches. Given a routing tree with its node degree bounded by a constant, our test generation algorithm runs in linear time with respect to the number of leaves of the tree. For probe route scheduling, we observe that in order to obtain a balanced and efficient scheduling, the routes of different probes must be considered simultaneously, which motivates our Multi-Dimensional Traveling Salesman Problem (MDTSP) formulation. Our package has been installed on existing substrate testers and has achieved encouraging results
Keywords :
fault location; hybrid integrated circuits; integrated circuit testing; multichip modules; network routing; probes; substrates; trees (mathematics); MCM substrate testing; high resistance faults; k-probe testers; multi-dimensional traveling salesman problem formulation; multi-probe approach; open faults; routing tree model; short faults; test generation algorithm; test size reduction; testing speed; throughput; wiring networks; Ceramics; Costs; Fault detection; Job shop scheduling; Packaging; Probes; Routing; Testing; Throughput; Wiring;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on