A low-power DS-CDMA RAKE receiver utilizing resource allocation techniques

This paper presents architectural and implementation innovations made to realize a self-contained front-end processor for any DS-CDMA-based system. At the heart of the ASIC is a highly flexible RAKE processing engine that utilizes a unique resource allocation technique for maximum flexibility. The front-end of the chip consists of a matched filter and an all digital timing and frequency recovery loop based on interpolation and direct digital frequency synthesis (DDFS) techniques. A highly configurable multipath combiner is used to generate the final demodulated symbols by combining contributions from different multipath in a maximal ratio combining scheme. The combiner is also instrumental in performing channel estimation/correction and in closing the loop on the timing and frequency recovery circuits. The chip also features a multipath searcher which performs an energy scan of the wireless channel to decide on new valid multipath. To minimize power consumption and enhance the flexibility of the architecture a unique data tagging technique is utilized to decouple the sampling rate of the incoming data from the processing frequency of different blocks of the ASIC. All resources are programmable via a microcontroller interface that provides firmware control over system resources. Furthermore, the architecture supports the concept of design reuse by enabling simple modular expansion as a means of increasing resources. The resulting layout area is 8.29 mm² in a 0.18-μm 1-poly 6-metal CMOS process and consists of 320000 equivalent gates. The core consumes a total of 4.032 mW in a typical load scenario including full demodulation of two RAKE fingers and simultaneous searching for new multipath.