DocumentCode :
1044103
Title :
FPGA implementation of multiplication-free complex division
Author :
Liu, J. ; Weaver, B. ; Zakharov, Y.
Author_Institution :
Univ. of York, York
Volume :
44
Issue :
2
fYear :
2008
Firstpage :
95
Lastpage :
96
Abstract :
The FPGA implementation of a new complex division algorithm is described. It is based on the dichotomous co-ordinate descent method and requires only bit-shift and addition operations. Consequently, the footprint of the new complex division core is remarkably small.
Keywords :
field programmable gate arrays; signal processing; FPGA; bit-shift; dichotomous coordinate descent method; multiplication-free complex division;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20082567
Filename :
4436135
Link To Document :
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