A cost analysis study for testability purposes on silicon active substrates

This paper presents cost analysis results based on yield calculations of test structures placed on multichip module (MCM) substrates. Calculations are made using yield analysis studies based on the number of defects per area, a critical technological-dependent parameter. The use of MCMs has increased in recent years thanks to their high integration capacity, their greater performance, the capacity to gather different technological integrated circuits (ICs) on the same substrate, and to the reduced substrate areas obtained. These characteristics make the MCMs a powerful integration technology for module development, but the intrinsic construction of the MCMs may cause significant problems when testing has to be performed. Because of this, new cost-effective test methodologies are expected for MCMs that will be built on the MCM substrate. These test structures on the MCM substrate will be integrated if cost-effective solutions are possible