• DocumentCode
    1045338
  • Title

    New SET Characterization Technique Using SPICE for Fully Depleted CMOS/SOI Digital Circuitry

  • Author

    Makihara, A. ; Ebihara, T. ; Yokose, T. ; Tsuchiya, Y. ; Amano, Y. ; Shindou, H. ; Imagawa, R. ; Takahashi, Y. ; Kuboyama, S.

  • Author_Institution
    High-Reliability Eng. & Components Corp., Tsukuba
  • Volume
    55
  • Issue
    6
  • fYear
    2008
  • Firstpage
    2921
  • Lastpage
    2927
  • Abstract
    The new SET characterization technique for 0.15 mum Fully Depleted CMOS/SOI digital circuitries was investigated using SPICE and TCAD simulations. The SPICE simulation with a switch can readily reproduce the corresponding SET voltage response for a certain LET. This technique is valid as an alternative in all load and complementary transistor conditions, irrespective of the presence of a plateau region in the SET current waveform generated in a struck transistor.
  • Keywords
    CMOS digital integrated circuits; silicon-on-insulator; LET; SET characterization technique; SOI digital circuitry; SPICE simulations; TCAD simulations; full depleted CMOS digital circuitry; singleevent transients; CMOS digital integrated circuits; CMOS logic circuits; Circuit simulation; Isolation technology; Logic devices; Pulse circuits; Pulse generation; SPICE; Switches; Voltage; Commercial process; SET; SEU; fully depleted CMOS/SOI; hardness-by-design;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2008.2007723
  • Filename
    4723724
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1045338