DocumentCode :
1045388
Title :
Quantifying the Effect of Guard Rings and Guard Drains in Mitigating Charge Collection and Charge Spread
Author :
Narasimham, Balaji ; Gambles, Jody W. ; Shuler, Robert L. ; Bhuva, Bharat L. ; Massengill, Lloyd W.
Author_Institution :
Vanderbilt Univ., Nashville, TN
Volume :
55
Issue :
6
fYear :
2008
Firstpage :
3456
Lastpage :
3460
Abstract :
3D-TCAD simulations in a 130-nm process are used to show the effect of guard rings and guard drains in mitigating charge collection and charge sharing between nodes. Experimental results quantifying the reduction in SET pulse width and the error cross section were obtained with the use of SET pulse width and SET error rate measurement test circuits fabricated in 130-nm and 180-nm processes. Results indicate that guard drains results in 30% lower error cross section compared to guard ring circuits.
Keywords :
integrated circuit measurement; integrated circuit testing; technology CAD (electronics); 3D-TCAD simulations; SET error rate measurement test circuits; error cross section; guard drains; guard ring circuits; guard rings; integrated circuits; size 130 nm; size 180 nm; Circuit testing; Costs; Fabrication; Integrated circuit noise; MOS devices; Microelectronics; Pulse circuits; Pulse measurements; Radiation hardening; Space vector pulse width modulation; Collected charge; Single-Event Transient (SET); guard drain; guard ring; pulse width; single event;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.2008.2007119
Filename :
4723730
Link To Document :
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