A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability

This paper presents a 20b clockless DAC designed for precision calibrated systems. The architecture is a 6b parallel resistor voltage divider with a 14b R-2R subDAC. This architecture is inherently good for noise and temperature stability. Major causes of nonlinearity are discussed. A single current-output calibration DAC corrects for both random resistor mismatch and systematic resistor nonlinearity. A force and sense switch topology overcomes INL from CMOS switch resistance. The DAC is implemented in a 0.6 μm 30 V BiCMOS process with 5 V CMOS devices and Si-Cr thin-film resistors. It achieves 0.33 ppm INL and 7.5 nV/√Hz noise with a ±10 V output span. It has 0.05 ppm/°C temperature stability and settles in 1 μs. Current consumption is 4.2 mA from 30 V supplies, excluding power required for external reference buffers.