Title :
Self-Voting Dual-Modular-Redundancy Circuits for Single-Event-Transient Mitigation
Author_Institution :
Sandia Nat. Labs., Albuquerque, NM
Abstract :
Dual-modular-redundancy (DMR) architectures use duplication and self-voting asynchronous circuits to mitigate single event transients (SETs). The area and performance of DMR circuitry is evaluated against conventional triple-modular-redundancy (TMR) logic. Benchmark ASIC circuits designed with DMR logic show a 10-24% area improvement for flip-flop designs, and a 33% improvement for latch designs.
Keywords :
application specific integrated circuits; asynchronous circuits; logic design; ASIC circuits designed; asynchronous circuits; dual-modular-redundancy architectures; flip-flop designs; latch designs; self-voting dual-modular-redundancy circuits; single event transients; single-event-transient mitigation; triple-modular-redundancy logic; CMOS logic circuits; Combinational circuits; Flip-flops; Latches; Logic circuits; Logic design; Logic devices; Registers; Sequential circuits; Voltage; Asynchronous circuits; combinational logic; sequential logic; single event effects;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2008.2005583
