• DocumentCode
    1045797
  • Title

    CMOS four-quadrant multiplier using bias offset crosscoupled pairs

  • Author

    Liu, Shen-Iuan ; Hwang, Y.-S.

  • Author_Institution
    Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan
  • Volume
    29
  • Issue
    20
  • fYear
    1993
  • Firstpage
    1737
  • Lastpage
    1738
  • Abstract
    A CMOS four-quadrant multiplier using bias offset crosscoupled pairs is presented. Simulation results show that a for a power supply of +or-5 V, the linearity error is less than 1% over a +or-2.5 V input range. The effect of mobility reduction is also analysed. The results will be useful in analogue signal processing applications.
  • Keywords
    CMOS integrated circuits; analogue processing circuits; linear integrated circuits; multiplying circuits; -5 to 5 V; CMOS; analogue signal processing applications; bias offset; crosscoupled pairs; four-quadrant multiplier; linearity error; mobility reduction; monolithic IC;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19931156
  • Filename
    274885
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1045797