Title :
CMOS four-quadrant multiplier using bias offset crosscoupled pairs
Author :
Liu, Shen-Iuan ; Hwang, Y.-S.
Author_Institution :
Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan
Abstract :
A CMOS four-quadrant multiplier using bias offset crosscoupled pairs is presented. Simulation results show that a for a power supply of +or-5 V, the linearity error is less than 1% over a +or-2.5 V input range. The effect of mobility reduction is also analysed. The results will be useful in analogue signal processing applications.
Keywords :
CMOS integrated circuits; analogue processing circuits; linear integrated circuits; multiplying circuits; -5 to 5 V; CMOS; analogue signal processing applications; bias offset; crosscoupled pairs; four-quadrant multiplier; linearity error; mobility reduction; monolithic IC;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19931156
