Realisation of high-speed systolic IIR decimators and interpolators

Two novel systolic allpass digital filtering arrays for realising high-speed systolic IIR decimators and interpolators are described. The sampling period at the input of such a decimator by N at the output of such an interpolator by N can be reduced to (T_m+2T_a)/(N-1) and (T_m+3T_a)/N, respectively, by the two arrays. (T_m and T_a, respectively, represent the times for two-input real multiplication and two-input real addition.) Other advantages include reduced latencies, and reduced numbers of multipliers and adders.