DocumentCode :
1046268
Title :
Tradeoffs in the design of efficient algorithm-based error detection schemes for hypercube multiprocessors
Author :
Balasubramanian, Vijay ; Banerjee, Prithviraj
Author_Institution :
Dept. of Electr. Eng., Illinois Univ., Urbana, IL, USA
Volume :
16
Issue :
2
fYear :
1990
fDate :
2/1/1990 12:00:00 AM
Firstpage :
183
Lastpage :
196
Abstract :
The authors provide an in-depth study of the various issues and tradeoffs available in algorithm-based error detection, as well as a general methodology for evaluating the schemes. They illustrate the approach on an extremely useful computation in the field of numerical linear algebra: QR factorization. They have implemented and investigated numerous ways of applying algorithm-based error detection using different system-level encoding strategies for QR factorization. Specifically, schemes based on the checksum and sum-of-squares (SOS) encoding techniques have been developed. The results of studies performed on a 16-processor Intel iPSC-2/D4/MX hypercube multiprocessor are reported. It is shown that, in general, the SOS approach gives much better coverage (85-100%) for QR factorization while maintaining low overheads (below 10%)
Keywords :
encoding; error detection; linear algebra; multiprocessing systems; software engineering; 16-processor Intel iPSC-2/D4/MX; QR factorization; algorithm-based error detection; checksum; encoding; hypercube multiprocessors; numerical linear algebra; sum-of-squares; Algorithm design and analysis; Computer architecture; Computer errors; Concurrent computing; Costs; Electrical fault detection; Fault detection; Hardware; Hypercubes; Parallel algorithms;
fLanguage :
English
Journal_Title :
Software Engineering, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-5589
Type :
jour
DOI :
10.1109/32.44381
Filename :
44381
Link To Document :
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