Title :
Three-mask self-aligned MOS technology
Author :
Mai, C.C. ; Chan, T.C. ; Palmer, R.B.
Author_Institution :
Mostek Corporation, Worcester, Mass.
fDate :
12/1/1973 12:00:00 AM
Abstract :
A three-mask process has been developed which permits one to fabricate MOSFET or integrated circuits with self-aligned gate, reduce capacitance, and flatter surface topology. Ion implantation and silicon nitride layers were employed in this process.
Keywords :
Cathodes; Coupling circuits; Electrons; Integrated circuit technology; MOSFET circuits; Noise figure; Optical coupling; Silicon; Surface topography; Temperature;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1973.17813
