Simulation of electrical overstress thermal failures in integrated circuits

Author

Díaz, Carlos H. ; Kang, Sung-Mo ; Duvvury, Charvaka

Volume

41

Issue

3

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

359

Lastpage

366

Abstract

Electrical overstress (EOS) and electrostatic discharge (ESD) pose the most dominant threats to integrated circuits (ICs) reliability. As a measure for EOS/ESD reliability, the power-to-failure versus time-to-failure relationship (power profile) has been recently proposed to determine the EOS failure thresholds of integrated circuits. This paper presents a nonlinear mixed 2D-1D thermal simulator, iTSIM, for ESD/EOS failure studies in ICs. iTSIM´s computational efficiency to handle large-scale EOS thermal problems in ICs derives from the special set of boundary conditions introduced in this paper. Simulated power profiles for various combinations of major thermal parameters of the IC die-package structure are shown to agree with experimental data

Keywords

boundary-value problems; circuit reliability; digital simulation; electronic engineering computing; electrostatic discharge; failure analysis; monolithic integrated circuits; semiconductor device models; thermal analysis; EOS; ESD; IC die-package structure; IC reliability; ITSIM; boundary conditions; electrical overstress thermal failures; electrostatic discharge; integrated circuits; nonlinear mixed 2D-1D thermal simulator; simulated power profiles; Circuit simulation; Computational efficiency; Computational modeling; Earth Observing System; Electrostatic discharge; Electrostatic measurements; Integrated circuit measurements; Integrated circuit reliability; Large-scale systems; Power measurement;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.275221

Filename

275221