Drain structure optimization for highly reliable deep submicrometer n-channel MOSFET

Author

Matsuoka, Fumitomo ; Kasai, Kunihiro ; Oyamatsu, Hisato ; Kinugawa, Masaaki ; Maeguchi, Kenji

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

Volume

41

Issue

3

fYear

1994

fDate

3/1/1994 12:00:00 AM

Firstpage

420

Lastpage

426

Abstract

A guideline for n^- fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, the greatest reduction in substrate current directly leads to the most reliable n^- design for the FOLD structure. The current path modulation phenomenon due to the trapped charge at the n ^- extension region dominates the hot-carrier induced characteristics change for conventional lightly doped drain (LDD) structure with side-wall spacer. This phenomenon is minimized in the FOLD structure due to its higher controllability of the gate electrode than the LDD structure at the n^- extension region. Furthermore, it was also confirmed that the 0.3 μm optimized FOLD structure can achieve high circuit performance at 3.3 V operation, maintaining hot-carrier resistance

Keywords

hot carriers; insulated gate field effect transistors; reliability; 0.3 micron; FOLD structure; deep submicrometer device; drain structure optimization; fully gate overlapped structure; n-channel MOSFET; reliability; submicron device; substrate current; Circuit optimization; Controllability; Degradation; Design optimization; Electrodes; Guidelines; Hot carriers; MOSFET circuits; Maintenance; Power dissipation;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.275229

Filename

275229