DocumentCode
1047962
Title
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach
Author
Kim, Taewhan ; Yonezawa, Noritake ; Liu, Jane W S ; Liu, C.L.
Author_Institution
Lattice Semicond. Corp., Milpitas, CA, USA
Volume
13
Issue
4
fYear
1994
fDate
4/1/1994 12:00:00 AM
Firstpage
425
Lastpage
438
Abstract
A new scheduling algorithm for dataflow graphs with nested conditional branches is presented. The algorithm employs a bottom-up approach to transform a dataflow graph with conditional branches into an “equivalent” one that has no conditional branches. A schedule is then obtained for the latter, using a conventional scheduling algorithm, from which a schedule for the former is derived. Our approach is particularly effective when there is a large number of nested conditional branches in a dataflow graph
Keywords
VLSI; circuit CAD; graph theory; logic CAD; resource allocation; scheduling; VLSI design; bottom-up approach; conditional resource sharing; dataflow graphs; hierarchical reduction approach; high level synthesis; nested conditional branches; scheduling algorithm; Adders; Arithmetic; Concurrent computing; Costs; Hardware; Processor scheduling; Resource management; Scheduling algorithm; Time factors; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.275353
Filename
275353
Link To Document