FinFET Design for Tolerance to Statistical Dopant Fluctuations

Variations in highly scaled (L _G = 9 nm), undoped-channel FinFET performance, caused by statistical dopant fluctuations (SDFs) in the source/drain (S/D) gradient regions, are systematically investigated using 3-D atomistic device simulations. The impact of SDF on device design optimization is examined and simple design strategies are identified. Variation-tolerant design imposes stringent specifications for S/D lateral abruptness and gate-sidewall spacer thickness, and it poses a tradeoff between performance and variability for body thickness.