DocumentCode
1047969
Title
FinFET Design for Tolerance to Statistical Dopant Fluctuations
Author
Varadarajan, Vidya ; Smith, Lee ; Liu, Tsu-Jae King
Author_Institution
Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY
Volume
8
Issue
3
fYear
2009
fDate
5/1/2009 12:00:00 AM
Firstpage
375
Lastpage
378
Abstract
Variations in highly scaled (L G = 9 nm), undoped-channel FinFET performance, caused by statistical dopant fluctuations (SDFs) in the source/drain (S/D) gradient regions, are systematically investigated using 3-D atomistic device simulations. The impact of SDF on device design optimization is examined and simple design strategies are identified. Variation-tolerant design imposes stringent specifications for S/D lateral abruptness and gate-sidewall spacer thickness, and it poses a tradeoff between performance and variability for body thickness.
Keywords
MOSFET; FinFET design; device design optimization; statistical dopant fluctuations; Atomistic simulation; FinFET; statistical dopant fluctuations (SDFs); variations;
fLanguage
English
Journal_Title
Nanotechnology, IEEE Transactions on
Publisher
ieee
ISSN
1536-125X
Type
jour
DOI
10.1109/TNANO.2008.2011731
Filename
4729647
Link To Document