DocumentCode
104798
Title
Using Selective Voltage Binning to Maximize Yield
Author
Lichtensteiger, Susan ; Bickford, Jeanne Paulette
Author_Institution
IBM Corp. Syst. & Technol. Group, Essex Junction, VT, USA
Volume
26
Issue
4
fYear
2013
fDate
Nov. 2013
Firstpage
436
Lastpage
441
Abstract
Yield loss associated with leakage screens is increasing as products migrate to technologies with thinner gate oxide and more aggressive lithography. Product competitiveness requires meeting low power and when products have exhausted design options, tighter than 3 sigma fast leakage screens are implemented to reduce power which can result in significant yield loss.
Keywords
design engineering; leakage currents; lithography; power integrated circuits; semiconductor technology; design; leakage screens; lithography; product competitiveness; product power reduction; selective voltage binning; yield loss; Capacitance; Leakage currents; Lithography; Performance evaluation; Product design; Yield estimation; IDDQ; Screen; voltage binning; yield;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/TSM.2013.2268392
Filename
6531674
Link To Document