A performance-driven logic emulation system: FPGA network design and performance-driven partitioning

FPGAs are widely used for logic emulation, software acceleration, custom computing, and prototyping. The architecture (or the interconnect mechanism of a FPGA network) of an emulator has profound effect on the performance (speed) and efficiency (chip utilization) of the emulator. In this paper, several architectures of FPGA networks are suggested, and they are compared with other typical existing architectures by using the MCNC partition benchmark circuits. Experimental results show that tripartite network outperforms six other typical architectures both in performance and in efficiency. For this study, the propagation delay of a path is estimated by the number of hops (interchip connections) and the number of intrachip connections on the path, and thus it is independent of a specific FPGA type. To partition a given circuit into the given prerouted network of FPGAs, a new routability-driven partitioning algorithm is developed. Experimental results using the MCNC benchmark examples show that our partition method produces better results than those of other recent approaches on the average, and that performance-driven partitioning is effective in reducing critical time delays